Physical ASIC Design Implementation Engineer

About the role

imec Qatar, a new regional office focused on advanced semiconductor design tools such as silicon photonics and 3D integrated circuits, is hiring a Physical ASIC Design Implementation Engineer in Doha. The digital chip design team covers the full flow from architecture through tapeout to the foundry, and the position joins the physical digital implementation group.

Key responsibilities

• Create GDSII files ready for production from RTL or netlist.
• Set up the flow for the chosen library set and foundry node.
• Handle low-power design (UPF), floorplanning and power grid design.
• Perform detailed timing-driven placement, STA and design optimisation, clock tree synthesis, scan chain re-stitching and detailed timing-driven routing including SI.
• Run IPOs to fix timing in all corners, solve setup and hold violations, and perform sign-off extraction, timing and power analysis.
• Carry out physical verification (DRC, ERC, LVS, ANT) and logic equivalence checks.
• Lead partitioning of the top-level SDC file into timing budgets and constraints for hierarchical designs.
• Work with other physical designers to close sign-off for tape-out and look for AI methods to speed up the flow.

Required profile

• Master's degree in Electronics.
• Experience in hierarchical physical implementation in advanced nodes with Synopsys or Cadence EDA tools.
• Experience with power reduction techniques such as gated clocks, voltage domains, memory retention and switch-off power domains.
• Experience debugging tool, flow and design issues.
• Excellent communication skills; English is mandatory.

Required skills

• Synopsys or Cadence EDA tools
• Place-and-route flow, STA, clock tree synthesis, physical verification (DRC, ERC, LVS)
• Power reduction techniques (UPF, gated clocks, voltage domains)