DFT ASIC Design Engineer

About the role

imec Qatar, a new regional office focused on advanced semiconductor design tools for silicon photonics and 3D integrated circuits, is looking for a DFT Engineer to join from day one in Doha. The role uses Design-for-Test expertise to make complex integrated circuits optimally testable, ensuring their testability, quality and performance.

Key responsibilities

• Architect DFT solutions for SOCs with multiple sub-blocks and complex soft/hard IPs, and coordinate and negotiate DFT requirements.
• Implement and validate innovative DFT techniques on SOCs and sub-systems, and define timing constraints for DFT test modes.
• Insert boundary scan, compression, MBIST/repair and on-chip clock controllers for large-scale low-power designs in advanced nodes (5nm and beyond).
• Generate test patterns, improve fault coverage, debug post-silicon test patterns, and diagnose memory and scan issues.
• Work with the physical design team on timing violations, signal/power integrity and routing congestion, and with the test engineering team on silicon characterization and validation.
• Adopt AI methodology to speed up work.

Required profile

• 5+ years of experience with DFT insertion and ATPG.
• Experience as a DFT owner of sub-systems, including insertion and verification of all DFT structures.
• Experience integrating DFT into complex PHY blocks (PCIe, UCIe, LPDDR5, etc.).
• Basic fluency in Verilog/VHDL to write test logic when needed.

Required skills

• Expert knowledge of IEEE 1149.1, 1149.6 and 1687 (IJTAG) standards and their file formats (ICL, PDL).
• Hands-on experience with SDC constraints and DFT insertion/verification in advanced nodes.
• EDA tools such as Tessent (Siemens), Genus/Modus (Cadence) and simulation tools; scripting languages such as TCL.
• Preferred: DFT flow definition/maintenance, IEEE1838, DFT for chiplets (2.5D/3D), and Tessent SSN.